mlir_aie wheel 版本必须与仓库 commit 及 requirements 严格匹配,否则易出现难调试的错误;需先装好 XDNA 驱动和 XRT 并把用户加入 render 组才能访问 NPU;需关闭 SecureBoot 并更新 BIOS 以启用 NPU。
mlir-aie
Xilinx活跃维护基于 MLIR 的开源编译器工具链,提供贴近硬件的 Python API,用来给 AMD Ryzen AI NPU(AI Engine)编写和编译算子程序。
A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.
source utils/env_install.sh
source utils/env_setup.sh需要带 NPU 的 AMD Ryzen AI 处理器(或 Versal AI Engine 设备),Linux 内核 6.17 或更新,并安装 XDNA 驱动与 XRT;README 未说明显存或 CPU 运行方式。
用 Python 直接编程 AMD Ryzen AI NPU 的 AI Engine 阵列,基于开源 MLIR 编译工具链
基于 MLIR 的开源编译器工具链,提供贴近硬件的 Python API,用来给 AMD Ryzen AI NPU(AI Engine)编写和编译算子程序。
核心能力
- 用 @iron.jit 装饰器把 Python 设计 JIT 编译成 xclbin 并运行在 NPU 上
- 通过 ObjectFifo 显式控制主机与计算 tile 之间的数据搬运
- 用 Worker 和 Runtime 手动指定 tile 放置与执行顺序
- 经 LLVM/MLIR 的 Peano 编译器生成 AIE 指令流
- 提供多级抽象 MLIR 表示,描述核心、数据移动与阵列连接
容易踩的坑
- v1.4.5最新正式版2026-11-03 · 2026-11-03 19:35 UTC
🧠 TL;DR
- ✅ Expanded IRON programming capabilities, ObjectFIFO fusion, and dynamic reconfiguration
- ✅ New YOLO26n NPU2 implementation, Llama 3.2 1B improvements, and attention kernels
- ✅ Faster compilation, lower host dispatch overhead, and improved kernel performance
- ✅ Expanded HSA packaging, CERT runtime sequencing, and tracing support
- ✅ Stronger DMA, routing, ObjectFIFO verification, and developer tooling
🔍 Highlights
🚀 IRON & Dynamic Runtime
- Added
ObjectFifoPool, support for multiple device configurations, and improved placement and runtime merging for on-chip operator fusion → @andrej, @hunhoffe - Expanded dynamic reconfiguration with a new programming example and benchmark, full-ELF initialization/teardown, and per-call DMA repeat counts → @andrej, @jskimko, @hunhoffe
- Added explicit route pinning via
aie.flow'sviaattribute and improved packet-flow routing to avoid arbiter deadlocks → @andrej, @hunhoffe - Improved ObjectFIFO lowering, runtime DMA task configuration, and dynamic-shape programming examples → @jgmelber, @atassis
⚡ Kernels, Models & Performance
- Implemented the full YOLO26n detector in a single NPU2 configuration, using a dataflow programming approach → @hunhoffe
- Improved Llama 3.2 1B A8W8 decode and prefill, and expanded attention kernels for AIE2/AIE2P → @hunhoffe
- Added and optimized softmax, argmax, attention, vision, and quantized kernels, alongside expanded AIE2P vector lowering → @hunhoffe, @atassis, @erwei-xilinx
- Reduced host dispatch overhead in
CachedXRTRuntimeand improved compilation time and peak memory usage for large fused designs → @hunhoffe
⚙️ Compiler, Runtime & Correctness
- Improved core stack sizing using compiler measurements and added support for preserving MLIR source locations from IRON/Python through
aieccfor better diagnostics → @hunhoffe - Expanded CERT runtime support with deterministic multi-microcontroller sequencing, global barriers, and DMA chain generation → @fifield
- Improved HSACO packaging with full-ELF kernel selection by name and AIE4 architecture support → @ypapadop-amd
- Strengthened ObjectFIFO, DMA, and routing verification, including detection of stalled loops, unsafe BD reuse, incomplete transfers, and routing deadlocks → @hunhoffe
- Expanded AIEVec lowering and numerical correctness for AIE2P, including shuffle, elementwise, transcendental, and contraction operations → @erwei-xilinx
🛠️ Developer Experience & CI
- Improved IRON Python API typing, compiler diagnostics, source locations, and standalone programming examples → @hunhoffe, @saadafsy
- Added a maintainer dashboard and expanded nightly kernel, routing, and compiler reliability checks → @hunhoffe
- Improved Windows CI, on-device test retries, Peano-only builds, and build-system reliability → @jgmelber, @andrej, @atassis, @hunhoffe
- Continued dependency updates, security hardening, and documentation cleanup → multiple contributors
⚠️ Migration Notes
- Compiler verification is stricter. Invalid ObjectFIFO, DMA, and routing configurations that previously compiled may now produce diagnostics.
- IRON Python APIs continue to evolve. Downstream users relying on internal APIs may need to accommodate ongoing changes to runtime, kernel, and ObjectFIFO abstractions.
🔭 Looking Ahead
Several programming-model areas remain under active development:
- Continued DMA lowering and verification consolidation may introduce changes or deprecation around
npu.dma_memcpy_nd. - ObjectFIFO APIs and lowering will continue evolving as restructuring and operator-fusion support progress.
- IRON Python APIs will continue expanding around dynamic runtime sequences, reconfiguration, and host-driven execution.
🙌 New Contributors
- @saadafsy
- @GeorgiaPreda
Thank you to everyone who contributed to the v1.4.5 release!
Full Changelog: https://github.com/Xilinx/mli
- v1.4.5-alpha.2pre-release2026-10-31 · 2026-10-31 04:00 UTC
这个版本没有写更新说明。
- v1.4.5-alpha.1pre-release2026-10-15 · 2026-10-15 22:09 UTC
查看更新说明
Alpha Release for IRON Model Testing
- v1.4.42026-10-06 · 2026-10-06 16:18 UTC
查看更新说明
v1.4.4
🧠 TL;DR
- ✅ Expanded dispatch-time programming and dynamic DMA capabilities in IRON
- ✅ Major kernel expansion and performance work
- ✅ Faster, more scalable
aiecccompilation and kernel caching - ✅ Improved memory/resource allocation, routing, and runtime correctness
- ✅ Continued Windows, tracing, and developer tooling improvements
🔍 Highlights
🚀 IRON & Dynamic Runtime
- Added
DispatchTime[T]runtime scalars, enabling one compiled IRON design to execute with different runtime values → @hunhoffe - Expanded runtime-sequence DMA to mem/core tiles with compiler-managed BD allocation, runtime-configurable shim DMA transfer lengths, and dynamic multi-BD chains → @hunhoffe, @erwei-xilinx
- Added a unified symbolic taplib representation for static and dispatch-time tensor access patterns → @hunhoffe
- Expanded explicit-DMA APIs with
DmaChannel.loop,Flow.fill/drain, and correctness fixes driven by downstream IRON usage → @hunhoffe - Added a Python HSACO packer for AIE kernels, expanding support for HSA-based packaging and deployment workflows → @ypapadop-amd
⚡ Kernels & Performance
- Added Flash Attention prefill kernels, additional narrow-query Flash Attention variants, channels-last depthwise convolution, and additional FastFlowLM Gemma 4 kernels → @hunhoffe, @asyms, @andrej
- Expanded AIE2P kernel coverage and demonstrated MobileNet using tuned kernels → @hunhoffe
- Added q4nx → bfp16ebs8 dequantization and additional sampling, matrix/vector, and activation kernels → @andrej, @hunhoffe
- Fixed AIEVec optimization regressions affecting bf16 GEMM and improved AIE2P lowering for vector operations → @erwei-xilinx
⚙️ Compiler & Runtime
- Fixed quadratic memory and compile-time scaling for large fused designs and added a kernel object cache to accelerate repeated compilation → @atassis, @hunhoffe
- Improved
aieccby assembling full ELFs in-process, eliminating unnecessary core IR copies, and improving post-link validation → @jgmelber, @hunhoffe - Improved memory allocation with spill-aware DMA resource allocation, static-table bank placement, and more accurate placement around reserved memory → @hunhoffe
- Made routing passes idempotent and strengthened validation for unsupported circuit-flow and control-packet routing configurations → @andrej
🛠️ Platform & Developer Experience
- Completed the migration and cleanup of IRON's C++ kernel library and added single-core kernel optimization and benchmarking infrastructure → @efurst, @andrej, @hunhoffe
- Improved tracing output and correctness, including multiple trace-buffer slices and synchronization wrap handling → @hunhoffe
- Improved Windows NPU CI and added caching for Windows Ryzen AI wheel builds → @jgmelber
- Continued JIT cache correctness, kernel-source handling, documentation, CI, and build-system improvements → multiple contributors
🔭 Looking Ahead
Several programming-model areas remain under active development:
- DMA lowering and verification consolidation may introduce API changes or deprecation around
npu.dma_memcpy_nd. - ObjectFIFO APIs and lowering will continue evolving as restructuring progresses.
- IRON Python APIs will continue expanding around dispatch-time values and dynamic runtime-sequence generation.
Thank you to everyone who contributed to the v1.4.4 release!
- v1.4.32026-09-11 · 2026-09-11 18:03 UTC
查看更新说明
v1.4.3
🧠 TL;DR
- ✅ Continued ObjectFIFO restructuring and dynamic runtime improvements
- ✅ Stronger DMA, memory, stack, and routing verification
- ✅ Improved compiler/JIT performance and kernel compilation
- ✅ Expanded host runtime, tracing, and platform support
- ✅ Continued build, CI, and developer tooling improvements
🔍 Highlights
🧩 ObjectFIFO, DMA & Runtime
- Continued ObjectFIFO restructuring, splitting lowering into smaller passes and operations for a more modular compiler pipeline → @andrej
- Expanded dynamic DMA support with out-of-order S2MM receivers on the runtime configuration path and safer separation of runtime and statically assigned BD IDs → @jskimko, @hunhoffe
- Added DMA dimension normalization and strengthened verification for BD fields, packet configuration, control-packet payloads, and runtime offsets → @xhmelon, @atassis, @hunhoffe, @jgmelber
- Improved runtime-sequence materialization for nested regions and fixed
dma_await_taskhandling of loop-carried values → @erwei-xilinx, @hunhoffe
⚡ Compiler, Memory & Performance
- Improved AIE memory modeling with exact buffer free-space tracking, per-core data regions, program-memory modeling, and call-graph-aware stack validation → @andrej @hunhoffe
- Improved compilation performance by compiling a design's kernels concurrently and deduplicating C++ AIE kernels → @atassis, @efurst
- Improved routing and placement to better account for port direction, DMA load, and packet-flow deadlock hazards → @erwei-xilinx, @atassis, @jgmelber
- Added
AIECC_JOBSto capaiecccompilation parallelism → @andrej
🛠️ Runtime, Platform & Developer Experience
- Added an HSA host runtime and improved HRX installation and runtime integration → @ypapadop-amd, @jtuyls, @Abhishek-Varma
- Added the VE3858 target model, improved NPU2/Gorgon Point support, and fixed Strix-family hardware context limits → @fifield, @atassis, @bong-water-water-bong
- Added tracing across multiple
aiex.runs and improved trace decoding correctness → @andrej, @atassis - Improved JIT cache correctness, deterministic kernel handling, and NPU availability diagnostics → @atassis, @hunhoffe
- Added a new AIE code-creation skill and continued CI, dependency, caching, and build-system improvements → @ypapadop-amd, multiple contributors
🔭 Looking Ahead
Several programming-model areas remain under active development:
- DMA lowering and verification consolidation may introduce API changes or deprecation around
npu.dma_memcpy_nd. - ObjectFIFO APIs and lowering will continue evolving as restructuring progresses.
- IRON Python APIs will continue expanding toward more ergonomic dynamic runtime-sequence generation.
🙌 New Contributors
- @bong-water-water-bong
- @shdu-amd
- @AngryLoki
Thank you to everyone who contributed to the v1.4.3 release!
用户点评
登录用户的真实使用记录,可按版本和硬件筛选还没有人点评。第一个说出真实体验的人最有价值。
IRON / MLIR-AIE
A close-to-metal Python API for programming AMD Ryzen™ AI NPUs, built on an open-source MLIR-based compiler toolchain.
📖 Documentation · 🚀 Programming Guide · 🐍 Python API · 💡 Examples · 📊 Dashboard
Write Python. Run it on the NPU. IRON compiles your Python design straight to the AI Engine array inside AMD Ryzen™ AI processors — you control tile placement, data movement, and vectorized compute, with nothing hidden behind a framework. Built for researchers and performance engineers pushing the NPU on everything from machine learning to digital signal processing, IRON complements mainstream inference tooling like the AMD Ryzen™ AI Software Platform rather than replacing it.
import aie.iron as iron
from aie.iron import ObjectFifo, Program, Runtime, Worker
from aie.iron.controlflow import range_
import numpy as np
data_ty = np.ndarray[(1024,), np.dtype[np.int32]]
@iron.jit
def vector_add_one(a_in, b_out):
of_in = ObjectFifo(data_ty, name="in") # host → compute tile
of_out = ObjectFifo(data_ty, name="out") # compute tile → host
def core_fn(of_in, of_out): # runs on one AIE core
a = of_in.acquire(1)
b = of_out.acquire(1)
for i in range_(1024):
b[i] = a[i] + 1
of_in.release(1); of_out.release(1)
w = Worker(core_fn, [of_in.cons(), of_out.prod()])
def sequence(a, b, in_h, out_h):
in_h.fill(a)
out_h.drain(b, wait=True)
rt = Runtime(sequence, [data_ty, data_ty, of_in.prod(), of_out.cons()])
return Program(iron.get_current_device(), rt, workers=[w]).resolve_program()
a = iron.arange(1024, dtype=np.int32, device="npu")
b = iron.zeros(1024, dtype=np.int32, device="npu")
vector_add_one(a, b) # JIT-compiles on first call, runs on the NPU, caches after
@iron.jit compiles the design to an xclbin + instruction stream via the
LLVM/MLIR-based Peano compiler and runs it
on the attached NPU. New to the concepts? Start with the
Programming Guide or the
Mini Tutorial.
This repository contains an MLIR-based toolchain for AI Engine-enabled devices, such as AMD Ryzen™ AI and Versal™. It generates low-level configurations for the AI Engine portion of these devices. AI Engines are organized as a spatial array of tiles, where each tile contains AI Engine cores and/or memories. The spatial array is connected by stream switches that route data between tiles, scheduled by their programmable Data Movement Accelerators (DMAs). The repository provides MLIR representations at multiple levels of abstraction to target AI Engine devices, enabling compilers and developers to program cores and describe data movement and array connectivity.
The Peano component extends LLVM with the AI Engine processor as a target architecture, enabling integration with compiler frontends such as clang. Developers can use the AIE API header library to write efficient vectorized AIE core code in C++ that Peano compiles.
IRON is described in the following paper:
E. Hunhoff, J. Melber, K. Denolf, A. Bisca, S. Bayliss, S. Neuendorffer, J. Fifield, J. Lo, P. Vasireddy, P. James-Roxby, E. Keller. "Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface". In 33rd IEEE International Symposium On Field-Programmable Custom Computing Machines, May 2025.
Ryzen™ AI host setup
| Host | Start here |
|---|---|
| Linux (Ubuntu) | Continue with the Linux setup below |
| Linux (non-Ubuntu) | Non-Ubuntu Linux Setup |
| Windows 11 | Native Windows Setup |
| Windows via WSL | Windows via WSL Setup |
Getting Started for AMD Ryzen™ AI on Linux
These instructions will guide you through everything required for building and executing a program on the Ryzen™ AI NPU, starting from a fresh bare-bones Ubuntu 24.04 or Ubuntu 24.10 install.
NOTE: If you are using a different Linux distribution, see the non-Ubuntu build guide. Please be aware that building for distributions other than Ubuntu is experimental. Support may vary.
Prerequisites
BIOS Settings
- Be sure you have the latest BIOS on your laptop or mini-PC that enables the NPU. See here.
- Turn off SecureBoot (Allows for unsigned drivers to be installed):
BIOS → Security → Secure boot → Disable
Linux Kernel
Ensure your system is running Linux kernel 6.17 or newer before installing these packages. On Ubuntu 24.04 you can verify this with:
uname -r
If your kernel is older than 6.17, upgrade it using your distribution's kernel update mechanism -- on Ubuntu:
sudo apt update
sudo apt install --install-recommends linux-generic-hwe-24.04
sudo reboot
Install the XDNA™ Driver and XRT
Install from upstream packages (Ubuntu 24.04 with Linux 6.17+)
Install the XDNA driver and XRT from the AMD PPA:
The packaged XRT only supports Python 3.12 for
pyxrt
sudo add-apt-repository ppa:amd-team/xrt
sudo apt update
sudo apt install libxrt2 libxrt-npu2 libxrt-dev libxrt-utils libxrt-utils-npu amdxdna-dkms
sudo reboot
Make sure you are in the
rendergroup to access the NPU:sudo usermod -aG render $USERYou may need to logout and log back in after modifying user groups.
If you are on a different Linux distribution or kernel not supported by the upstream packages, see Build from source below. For non-Ubuntu distros (Arch, Void, Fedora-from-source, …) or kernels that already ship the in-tree
amdxdnadriver (Linux ≥ 6.14), see the non-Ubuntu build guide.
Verify the NPU device is present:
xrt-smi examine
At the bottom of the output you should see:
Devices present BDF : Name ------------------------------------ [0000:66:00.1] : NPU Strix
Install IRON and MLIR-AIE Prerequisites
Install the following packages needed for MLIR-AIE:
# Python versions 3.11, 3.12, 3.13, and 3.14 are currently supported by our wheels
sudo apt install \
build-essential clang clang-14 lld lld-14 cmake ninja-build python3-venv python3-pip uuid-dev
(Optional) Install opencv which is needed for vision programming examples:
sudo apt install libopencv-dev python3-opencv
Install IRON for AMD Ryzen™ AI AIE Application Development
From Pre-Built Binaries (Wheels)
Set up and source a Python virtual environment and install the IRON library
(mlir-aie wheel), and per-core compiler ("peano", llvm-aie wheel). The
following is the quickest path:
source utils/env_install.sh # one time / first time
source utils/env_setup.sh # every time you open a new shell
This creates an environment named ironenv containing the toolchain.
By default, the script will match the mlir_aie wheel associated with the
currently checked-out release/commit of the repository. If it can't find a
release for this commit, it will error, since trying to compile a version of
the programming examples in this repository with a compiler wheel whose version
does not exactly match very frequently leads to hard-to-debug errors. If you
insist on using the latest available release from main, pass --latest. To
manually install a different wheel, follow the manual instructions below.
Tip: The
utils/env_install.shscript also works as an update script.
From Source
To build the compiler toolchain from source, you'll need additional dependencies. Install the requirements using:
source utils/env_install.sh --dev # one time / first time
source utils/env_setup.sh # every time you open a new shell
Then, build the compiler (_from_wheels.sh in this case refers to the LLVM
installation being pulled from a wheel; MLIR-AIE links against LLVM, but will
be built from source):
./utils/build-mlir-aie-from-wheels.sh
Manual Installation Steps
Below steps replicate what the install script does.
-
Setup a virtual environment:
python3 -m venv ironenv source ironenv/bin/activate python3 -m pip install --upgrade pip -
Install IRON library by installing the
mlir-aiewheels:For installing the
mlir-aiewheels, there are 3 options. Note that for whichever path you take, it is important to sync themlir-aiewheels version, the GitHub repo commit, and the requirements versions. If you install from something other than the latest wheels, make sure you use the repo commit -- and installation instructions -- from that point in time.-
Latest: For the latest wheels (not necessarily a release):
# Install IRON library and mlir-aie from the latest wheel python3 -m pip install mlir_aie -f https://github.com/Xilinx/mlir-aie/releases/expanded_assets/latest-wheels-4 -
Latest Release: Alternatively, you can install the latest released version of
mlir-aie.# Get the latest release version latest_tag_with_v=$(curl -s "https://api.github.com/repos/Xilinx/mlir-aie/releases/latest" | jq -r '.tag_name') latest_tag="${latest_tag_with_v#v}" # Install IRON library and mlir-aie from the latest stable release python3 -m pip install mlir_aie==${latest_tag} -f https://github.com/Xilinx/mlir-aie/releases/expanded_assets/${latest_tag_with_v} git checkout $latest_tag_with_v -
Any Release: You can install a specific version of
mlir-aiefrom the release wheels. To see available versions, check out the release page.# Install IRON library and mlir-aie from a specific release, # e.g., <version> in the following command could be replaced with v1.1.3 python3 -m pip install mlir_aie -f https://github.com/Xilinx/mlir-aie/releases/expanded_assets/<version> git checkout <version>
-
-
Install the Peano compiler (the
llvm-aiewheels) and dependencies:# Install Peano from the llvm-aie wheel, pinned to the tested nightly in # utils/peano-requirements.txt (the same pin CI uses; bumped by the update-peano # workflow). To grab the latest nightly instead, install `llvm-aie` directly # with `-f https://github.com/Xilinx/llvm-aie/releases/expanded_assets/nightly`. python3 -m pip install -r utils/peano-requirements.txt -
(Optional) Install Python packages required for development and testing:
# Install Python requirements for development and testing python3 -m pip install -r python/requirements_dev.txt # Install the pre-commit and pre-push hooks defined in .pre-commit-config.yaml # (pre-push runs clang-format/black/ruff to catch formatting and lint issues before CI) pre-commit install -
Setup environment
source utils/env_setup.sh -
(Optional) Install ML Python packages for ml programming examples:
# Install Torch for ML examples python3 -m pip install -r python/requirements_ml.txt -
(Optional) Install Jupyter Notebook Python packages:
# Install Jupyter Notebook python3 -m pip install -r python/requirements_notebook.txt # This creates an ipykernel (for use in notebooks) using the ironenv venv python3 -m ipykernel install --user --name ironenv # Only for Release v1.0 and non wheel-based installs: # The install generally captures in the $PYTHONPATH by the `env_setup.sh` script. # However, jupyter notebooks don't always get access to the PYTHONPATH (e.g., if they are run with # vscode) so we save the ${MLIR_AIE_INSTALL_DIR}/python in a .pth file in the site packages dir of the # ironenv venv; this allows the iron ipykernel to find the install dir regardless of if PYTHONPATH is # available or not. MLIR_AIE_INSTALL="$(pip show mlir_aie | grep ^Location: | awk '{print $2}')/mlir_aie" venv_site_packages="$(python3 -c 'import sysconfig; print(sysconfig.get_paths()["purelib"])')" echo "${MLIR_AIE_INSTALL}/python" > "$venv_site_packages/mlir-aie.pth"
Run an IRON Design on the AMD Ryzen™ AI NPU on Linux
The programming examples use either of two entry points. Most examples use standalone @iron.jit to compile, run, and verify directly from Python:
cd programming_examples/<category>/<example>
python3 <example>.py
Examples with a separate native host, explicit artifact builds, or multi-stage workflow have a Makefile. Follow the example's README for its supported targets, such as make run or make run_py.
Learn more about NPU programming with IRON
-
Continue to the IRON AIE Application Programming Guide
-
Additional MLIR-AIE documentation is available on the website
-
AIE API header library documentation for single-core AIE programming in C++ is available here
-
If you are a university researcher or student and interested in trying these tools on our Ryzen™ AI AUP Cloud systems, please visit the AMD University Program
-
Have a question or want to talk with the team and other users? Join the ROCm Discord and look for the ROCm-NPU channel
Optional: Install AIETools
You may skip the Vitis™ installation step if you intend to only target AMD XDNA™/AIE-ML (AIE2) and AMD XDNA™ 2 (AIE2P) using our open-source single-core compiler Peano. Compiling with
xchessccis not supported without installing AMD Vitis™ AIE Essentials.
-
Install Vitis™ AIE Essentials from Ryzen AI Software 1.3 Early Access. We will assume you use the installation directory,
/tools/ryzen_ai-1.3.0/vitis_aie_essentials.This is an early access lounge, you must register and be granted access at this time.
-
Download VAIML Installer for Linux based compilation:
ryzen_ai-1.3.0ea1.tgz -
Extract the required tools:
tar -xzvf ryzen_ai-1.3.0ea1.tgz cd ryzen_ai-1.3.0 mkdir vitis_aie_essentials mv vitis_aie_essentials*.whl vitis_aie_essentials cd vitis_aie_essentials unzip vitis_aie_essentials*.whl
-
-
Set up an AI Engine license.
-
Get a local license for AI Engine tools from https://www.xilinx.com/getlicense.
-
Copy your license file (Xilinx.lic) to your preferred location, e.g.
/opt/Xilinx.lic:
-
-
Setup your environment using the following script for Vitis™ for AIETools:
#!/bin/bash ################################################################################# # Setup Vitis AIE Essentials ################################################################################# export AIETOOLS_ROOT=/tools/ryzen_ai-1.3.0/vitis_aie_essentials export PATH=$PATH:${AIETOOLS_ROOT}/bin export LM_LICENSE_FILE=/opt/Xilinx.lic
Alternative: Build XDNA™ Driver and XRT from source
If the upstream packages do not support your kernel or distribution, you can build the driver and XRT from source:
-
Execute the scripted build process:
This script will install package dependencies, build the xdna-driver and xrt packages, and install them. These steps require
sudoaccess.bash ./utils/build_drivers.sh -
Reboot as directed after the script exits.
sudo reboot -
Check that the NPU is working if the device appears with xrt-smi:
source /opt/xilinx/xrt/setup.sh xrt-smi examine
Troubleshooting
Update BIOS
Be sure you have the latest BIOS for your laptop or mini PC, this will ensure the NPU (sometimes referred to as IPU) is enabled in the system. You may need to manually enable the NPU:
Advanced → CPU Configuration → IPU
NOTE: Some manufacturers only provide Windows executables to update the BIOS, please do this before installing Ubuntu.
Detailed Getting Started Guides and Documentation
IRON AIE Application Programming Guide
AMD XDNA NPU Architecture Cheatsheet — device/tile layout, memory hierarchy, vector register widths, MMUL shapes and divisibility constraints, routing/placement limits, and per-tile performance ballparks
AIE C++ Kernel Intrinsics Cheatsheet — AIE API boilerplate, loop-pipelining annotations, vector load/store, MMUL usage, and common intrinsic quick-reference tables
Working with a coding agent instead? The Agent Skills in this repo teach an agent (e.g. Claude Code) to write and optimize IRON designs the same way the Programming Guide teaches a person — see Agentic Programming for how the two fit together.
Building mlir-aie tools from source
MLIR Dialect and Compiler Documentation
Interested in contributing MLIR-AIE? Information for developers
See our Roadmap for where the project is headed, and our Security Policy for how to report vulnerabilities.