API changes and additions

• Enum names of the Alpha architecture are now correctly all upper case. Because of an old Auto-Sync bug all the enum names were prefixed with Alpha instead of ALPHA and some contained lower case letters. Sadly, I just recently recognized that Alpha was effected by that bug.

  While this change is very annoying for everybody using the Alpha module, it must be done before the Beta release. Please excuse the inconvenience!

  A simple command to replace almost all of these occurrences in your code base is:

  find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} +
  

  Author: @Rot127

• RISC-V got a v5 compatibility macro for its header. With its recent module update CS_MODE_RISCVC was renamed to CS_MODE_RISCV_C to be more consistent with the other CS_MODE_ enums. This could break builds against a v5 code base which only has CS_MODE_RISCVC.

  Now you can simply define CAPSTONE_RISCV_COMPAT_HEADER before including capstone.h and CS_MODE_RISCVC will be defined as alias for CS_MODE_RISCV_C

  #define CAPSTONE_RISCV_COMPAT_HEADER
  #include <capstone/capstone.h>
  

  Author: @moste00

• Prevent literal displacement truncation for AArch64 memory operands. There are AArch64 displacements which are 64bit in size. But aarch64_op_mem.disp was an int32_t. It was promoted to an int64_t. Author: @amaanmujawar

• Fixed several decoding bugs in the Alpha module. See https://github.com/capstone-engine/capstone/pull/2967 for details. Author: @mattst88

• The RISC-V details now also include the FP rounding mode cs_riscv.rounding_mode. Author: @moste00

• AArch64: Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM flag to print shifted MOVN and MOVZ instructions in their explicit forms instead of using the equivalent MOV aliases.

  Example output from cstool:

  > cstool aarch64 0xe402a012
  mov w4, #-0x170001
  
  > cstool aarch64+explicitwideimm 0xe402a012
  movn w4, #0x17, lsl #16
  
  > cstool aarch64+explicitwideimm 0xe402a052
  movz w4, #0x17, lsl #16
  

  Author: @amaanmujawar

• M68K: Fixed EA decoding error and added ColdFire EMAC_B dual-acc MAC. Author: @b1llow

Switch from v5 to v6

Please check out our release guide to get an overview what changed, improved, and how the transition can be made as painless as possible: https://github.com/capstone-engine/capstone/blob/next/docs/cs_v6_release_guide.md

What's Changed

• Add CI job for building and testing on 32bit big endian by @trufae in https://github.com/capstone-engine/capstone/pull/2941
• Fixed CONTRIBUTING.md not listing all Architectures by @rectrap in https://github.com/capstone-engine/capstone/pull/2952
• Find writeback registers by @slate5 in https://github.com/capstone-engine/capstone/pull/2960
• m68k: fix off-by-one bounds check in M68K_insn_name by @jmestwa-coder in https://github.com/capstone-engine/capstone/pull/2964
• Fix OOB reads/writes - CVE-2026-55893 & CVE-2026-55894 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2968
• Alpha: fix decoder bugs and add test coverage by @mattst88 in https://github.com/capstone-engine/capstone/pull/2967
• Fix crash due to invalid register by @moste00 in https://github.com/capstone-engine/capstone/pull/2966
• Fix naming convention for Alpha enums by @Rot127 in https://github.com/capstone-engine/capstone/pull/2971
• Add frm operands to float/double instructions by @moste00 in https://github.com/capstone-engine/capstone/pull/2972
• Apply clang-format by @Rot127 in https://github.com/capstone-engine/capstone/pull/2975
• Fix AArch64 predicate-as-counter register printed in hex by @yufengzjj in https://github.com/capstone-engine/capstone/pull/2976
• SH: fix signed shift overflow in sh_disassemble dsp decode by @jmestwa-coder in https://github.com/capstone-engine/capstone/pull/2983
• Guard

What's Changed

• Fix GHSA-5m9f-vqcm-g5pr and GHSA-jrw4-wj52-2vw8 found by @sondt99
• Add pre-release version to capstone.h

Full Changelog: https://github.com/capstone-engine/capstone/compare/6.0.0-Alpha8...6.0.0-Alpha9

What's Changed

• Set correct version number in CS_VERSION_EXTRA.
• Backports of CVE fixes and #2935 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2937

Full Changelog: https://github.com/capstone-engine/capstone/compare/5.0.8...5.0.9

Highlights

This is a patch release with bug fixes and a few new additions.

Thanks a lot to all the new contributors helping with this release!

Python Bindings

• Python bindings on Linux load libcapstone.so now with the RTLD_DEEPBIND flag set. On some Linux systems this should limit the symbols' scopes to the library, instead of global ones. Useful for tools which have two different Capstone versions in their dependency tree.

Architectures

• Update M68k and add support for ColdFire ISA (Sponsored by RizinOrg)
• Extend M680X support to RS08 and HCS12X.
• RISC-V: Add reg_access to details.
• Add support for x86 MOVSXD instructions.
• x86 decoding uses lookup tables now to increase the overall speed.

What's Changed

• wasm: add missing error check in read_memoryimmediate() by @Oblivionsage in https://github.com/capstone-engine/capstone/pull/2866
• Extend M680X support to RS08 by @historicattle in https://github.com/capstone-engine/capstone/pull/2872
• Python binding: Removing xprint utility used in the tests in v6 branch by @Antelox in https://github.com/capstone-engine/capstone/pull/2874
• Introduce a +noaliascompressed option to selectively enable none-aliasing for compressed instrcution only but leave aliasing for the rest of instructions by @moste00 in https://github.com/capstone-engine/capstone/pull/2869
• riscv: remove extra RISCV_INS_INVALID by @12101111 in https://github.com/capstone-engine/capstone/pull/2876
• update clang-format to 20 by @b1llow in https://github.com/capstone-engine/capstone/pull/2883
• cs_disasm_iter: return early on zero-size input by @slate5 in https://github.com/capstone-engine/capstone/pull/2886
• Fix stale values in the detail struct by @slate5 in https://github.com/capstone-engine/capstone/pull/2881
• Add dependabot.yml by @Rot127 in https://github.com/capstone-engine/capstone/pull/2884
• x86: correctly handle XACQUIRE/XRELEASE by @jxors in https://github.com/capstone-engine/capstone/pull/2882
• fix: avoid strnlen() in cs_strndup for Mac OS X 10.5 portability by @Scottcjn in https://github.com/capstone-engine/capstone/pull/2889
• Fix RISCV aliases by @slate5 in https://github.com/capstone-engine/capstone/pull/2891
• Document the test boolean values. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2892
• x86: simplify REX prefix parsing by @jxors in https://github.com/capstone-engine/capstone/pull/2885
• Fix sysreg registers in RISC-V and modify the header patcher to not crash if a header doesn't include all tags of a generated .inc file by @moste00 in https://github.com/capstone-engine/capstone/pull/2894
• RISC-V: add reg_access and test its usages in C and Python by @moste00 in https://github.com/capstone-engine/capstone/pull/2895
• RISCV: Fix operand detection (REAL/ALIAS) by @slate5 in https://github.com/capstone-engine/capstone/pull/2897
• Coverity fixes by @Rot127 in https://github.com/capstone-engine/capstone/pull/2901
• Update m68k by @b1llow in https://github.com/capstone-engine/capstone/pull/2880
• Fix position of comments to not break const_generator.py by @historicattle in https://github.com/capstone-engine/capstone/pull/2906
• Extend M680X support to HCS12X by @historicattle in https://github.com/capstone-engine/capstone/pull/2898
• next: Speedup x86 decoding with the help of LUT tables by @trufae in https://github.com/capstone-engine/capstone/pull/2908
• Implements load libcapstone.so with RTLD_DEEPBIND #2912 by @AGhebrea in https://github.com/capstone-engine/capstone/pull/2913
• Replace cmake setup with manual steps to reduce dependencies. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2916
• Python: use setattr to rewire Cs.disasm to avoid type checking errors by @mrexodia in https://github.com/capstone-engine/capstone/pull/2915
• Handle SStream overflow by truncating appends by @Rot127 in https://github.com/capstone-engine/capstone/pull/2921
• RISCV: the Ventana vendor is mi