安装步骤需查阅在线文档，README 未直接提供命令；当前后端仅覆盖 AMD/Intel FPGA 和 AMD Ryzen NPU，GPU/ASIC 尚未支持；使用编码代理时需导入 AGENTS.md
README 未给出安装命令，仅指向官方文档安装页：https://cornell-zhang.github.io/allo/setup/index.html 硬件要求按 README 说明
README 未说明具体显存或 CPU 要求；后端目标为 AMD 和 Intel FPGA 以及 AMD Ryzen NPU（AI Engine），GPU 与 ASIC 支持尚在计划中。
基于 MLIR 的 Python 嵌入式加速器设计与编程语言，用于模块化构建高性能 ML 加速器
面向 ASIC、FPGA 和 NPU 的加速器设计与编程框架，用 Python DSL 描述硬件，再经编译器生成高性能硬件实现。
核心能力
- 支持行为级与结构级组合，可增量搭建加速器系统
- 从 PyTorch 模型自动生成加速器
- 集成高性能模拟器与形式化验证器
- 后端支持 AMD/Intel FPGA 与 AMD Ryzen NPU
容易踩的坑
内容由模型根据 README 生成，可能不完整或不准确，以官方文档为准。看原文 README
暂无 release 数据（可能没有发版，或尚未同步）。
用户点评
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Accelerator Design and Programming Language
Documentation | Installation | Tutorials
Allo is a Python-embedded, MLIR-based language and compiler designed to facilitate the modular and composable development of large-scale, high-performance machine learning accelerators. It provides a unified abstraction for both accelerator design and programming, enabling developers to express complex architectures in a structured and reusable manner. Allo offers several key features:
- Composable Design and Programming: Allo supports both behavioral and structural composition, allowing users to incrementally build and compose accelerator components into a complete system with minimal overhead.
- End-to-End Deployment: Allo enables automatic accelerator generation from PyTorch models and integrates tightly with a high-performance simulator and a formal verifier, streamlining validation, testing, and deployment workflows.
- Multiple Backend Support: Allo currently targets AMD and Intel FPGAs as well as AMD Ryzen NPUs (AI Engine), with planned support for GPUs and ASICs in future releases.
Getting Started
Please check out the Allo documentation for installation instructions and tutorials. If you encounter any problems, please feel free to open an issue.
IMPORTANT: If you are using a coding agent for our codebase, please import AGENTS.md.
Publications
Please refer to our PLDI'24 paper for more details. If you use Allo in your research, please cite our paper:
Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, and Zhiru Zhang, "Allo: A Programming Model for Composable Accelerator Design", Proc. ACM Program. Lang. 8, PLDI, Article 171 (June 2024), 2024.
Please also consider citing the following papers if you utilize specific components of Allo:
- Dataflow programming model: Shihan Fang, Hongzheng Chen, Niansong Zhang, Jiajie Li, Han Meng, Adrian Liu, Zhiru Zhang, "Dato: A Task-Based Programming Model for Dataflow Accelerators", arXiv:2509.06794, 2025.
- AIE backend: Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou, "ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines", International Symposium on Field-Programmable Gate Arrays (FPGA), 2025. (Best paper nominee)
- Equivalence checker: Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, Zhiru Zhang, "Formal Verification of Source-to-Source Transformations for HLS", International Symposium on Field-Programmable Gate Arrays (FPGA), 2024. (🏆 Best Paper Award)
- LLM accelerator: Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang, "Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference", ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024. (FCCM’24 Journal Track) (🏆 ACM TRETS 2026 Best Paper Award)